Storage system using comparison and merger of encached data and update data at buffer to cache to maintain data integrity

ABSTRACT

A storage system includes a storage for storing data, and a store buffer for temporarily buffering data before storing it into the storage. A store request is applied to the store buffer, and store data accompanied by the store request is applied to the store buffer. When a fetch request for the storage does not exist, the store data buffered in the store buffer is transferred from the store buffer to the storage and is stored therein.

BACKGROUND OF THE INVENTION

The present invention relates to a storage system having store databuffering means. More particularly, it relates to a storage system wellsuited to a data processing system which includes a cache for retainingcopies of some of the data retained in a main storage and which iscontrolled by a pipeline system wherein "fetch" and "store" operationsare simultaneously generated for the cache.

Storages (a main storage and a cache) in a data processing system arecontrolled to perform the respective operations of fetching data,namely, an instructon and operands, and of storing an operand obtainedas the result of instruction execution. Further, since the cache has thecharacter of a copy of the main storage, the "store" operation involvingdata storage into a buffer storage occurs therein on the basis of aso-called block transfer in which a block composed of a certain numberof bytes is fetched from the main storage and registered in the bufferstorage. In the cache in a data processing system of the type which iscapable of pipeline operation, these operations of instruction fetch,operand fetch, store and block transfer can occur at the same time.Requests therefor are given priority levels, and when they occur, thebuffer storage is accessed in the order of (1) block transfer, (2)store, (3) operand fetch and (4) instruction fetch. When such requestsfor access to the cache are in contention, the processing of the lowpriority level is deferred to slow the instruction processing.

In order to lessen the contention of the access requests for the cache,an improved system has also been proposed in which the first half of onemachine cycle is allotted to the store of data into the cache, and thelatter half thereof is allotted to the fetch of data from the cache, soas to prevent contention between the store operation and the operand orinstruction fetch operation from arising. This system, however, has theproblem that the access time for the cache becomes equal to a halfmachine cycle, so cache constituents of high speed are required.

Japanese Patent Application Publication No. 53-24260 discloses a dataprocessing system which avoids the competition of requests for access toa cache. This system, however, does not disclose a technique forreducing the contention between a store request and a fetch requestwhich may arise from a data processing unit.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a storage system whichlessens the contention between "store" and "fetch" operations for astorage.

The storage system of the present invention comprises storage means forstoring data, and store buffer means for temporarily buffering storedata for the storage means before the data is stored in the storagemeans. The store data buffered in the store buffer means is stored inthe storage means when no fetch request exists for the storage means.

In a preferred embodiment of the present invention, when the amount ofstore data buffered in the store buffer means has reached apredetermined amount, for example, when the store buffer means has beenfilled up, the store buffer means transfers, even with the existence ofa fetch request for the storage means, the buffered store data into thestorage means with priority given thereto over the fetch request.

Since the present invention is so constructed as to temporarily bufferthe store data in the store buffer means before storing it in thestorage means, store data corresponding to data to be fetched can existin the store buffer means as data of the same address at the time of thefetch request. In a preferred embodiment of the present invention,therefore, the data is fetched from the storage means in response to thefetch request, and when the store data corresponding to the fetchrequest exists in the store buffer means, the store data is also fetchedfrom the store buffer means, and both the data items are merged into asingle fetch data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an embodiment of the presentinvention;

FIG. 2 is a block diagram showing the details of the cache in FIG. 1;

FIG. 3 is a block diagram showing the details of the store buffer inFIG. 2;

FIG. 4 is a block diagram showing the details of the input controller inFIG. 3;

FIG. 5 is a block diagram showing the details of the buffer in FIG. 3;

FIG. 6 is a block diagram showing the details of the selector in FIG. 5;

FIG. 7 is a block diagram showing the details of the output controllerin FIG. 3; and

FIG. 8 is a block diagram showing the details of the selector in FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 illustrates the exchange of signals (interfaces) between anexecution unit 1, a main storage 2 and a cache 3, and provides only thesignals pertinent to the present invention. Lines 4-7 carry a group ofsignals concerning the "store" operation, in which the line 4 carries astore request, the line 5 carries a store address, the line 6 carries astore mark, and the line 7 carries store data. The store mark indicatesa byte position or positions, within a plurality of bytes of the storedata to be stored, identifying the byte or bytes for which the storeoperation is to be performed. Assuming by way of example that the storedata depth of the cache is 8 bytes, the store mark is composed of 8bits, and the store operation is executed with respect to the byte orbytes corresponding to that bit or bits of the store mark which have thevalue "1". In case of re-storing all the 8 bytes of data, all the 8 bitsof the store mark are "1".

Lines 8, 9 and 11 carry a group of signals concerning the "operandfetch" operation, in which the line 8 carries an operand fetch request,the line 9 carries an operand address, and the line 11 carries theoperand fetch data. A line 10 carries a reset signal, which resetscontrol flip-flops in the cache 3. The lines 4-10 are the lines carryingsignals or data which are sent from the execution unit 1 to the cache 3,whereas the line 11 is the signal representing the data which is sentfrom the cache 3 to the execution unit 1. A line 12 and a line 13 form acontrol line and a data line concerning the block transfer and storeoperation for storing blocks of data in the main storage 2.

FIG. 2 shows the details of the cache 3 in FIG. 1. The cache 3 isconstructed of a buffer storage 15 as original storage means, a storebuffer 14, and a selector 16. The store data from the execution unit 1to the cache 3 is first stored and temporarily buffered in the storebuffer 14, and then is transferred from the store buffer 14 into thebuffer storage 15.

The buffer storage 15 is a memory which is small in capacity and high inspeed as compared with the main storage 2, and which holds as copiessome of the data retained by the main storage 2. Accordingly, when datarequested exists in the buffer storage 15, the data processing unit 1can fetch the data from the buffer storage 15 faster than in the case ofutilizing the data retained in the main storage 2.

In FIG. 2, lines 4-11 are the same as those lines 4-11 in FIG. 1. Lines17-19 are control lines and line 20 is a data line, each of these lines17-20 being concerned with the store of signals or data which is sentfrom the store buffer 14 to the buffer storage 15. The line 17 carries awrite pulse for store data, the line 18 carries a store address, theline 19 a store mark, and the line 20 the store data. Only when the line17 is "on", will the operand on the line 20 specified by the line 19 bestored into the location of the buffer storage 15 specified by the line18. Each of the lines 8 and 9 is also connected to the buffer storage15, and when an operand fetch request is issued, the line 8 turns "on",to fetch an operand onto a line 21 from the location of the bufferstorage 15 specified by the line 9. In the case where the operandrequested to be fetched is queuing in the store buffer 14, theparticular operand and the corresponding store mark are fetched from thestore buffer 14 onto a line 23 and a line 22, respectively. At thistime, the operand requested to be fetched is simultaneously fethed fromthe buffer storage 15 onto the line 21. Herein, within the operand onthe line 21 only the byte parts which correspond to "0" in the storemark on the line 22 are valid. The byte parts which correspond to the"1" positions of the store mark are extracted from the operand which isprovided on the line 23. The selection of the lines 21 and 23 dependentupon the store mark is performed by the selector 16. This is based onthe fact that, since those parts of the operand in the store buffer 14which correspond to "1" in the store mark represent valid data waitingto be stored in the buffer storage 15 to update what is stored in thebuffer storage 15, the operand on the line 23 needs to be used for thosebyte parts which correspond to "1" in the store mark if a fully-validoperand is to be fetched.

FIG. 3 illustrates the details of the store buffer 14. In FIG. 3, lines4-10 are the same as those lines similarly identified in FIGS. 1 and 2,and lines 17-20 and lines 22,23 are the dame as those lines similarlyidentified in FIG. 2. A buffer 25 has a plurality of registers forqueuing the address, mark, data, etc., of the store. An input controller24 designates the number of the register in the buffer 25 to receive aninput, and informs the buffer 25 of this through a line 27. The buffer25 determines the register to receive an input by means of this inputpointer. An output controller 26 designates the number of the registerin the buffer 25 to deliver an output, and informs the buffer 25 of thisthrough a line 28. The buffer 25 determines the register to deliver anoutput by means of this output pointer.

When the store request exists (the line 4 is "on"), the store address(on the line 5) is compared with address parts held by the group ofregisters in the buffer 25. In case of coincidence, the line 29 turns"on" to indicate that the store operand to be inputted to the buffer 25anew is already queuing in one of the registers within the buffer 25.The lines 29 are equal in number to the number of registers in thebuffer 25. When one of the lines 29 has turned "on", the input pointer27 specifies the register which corresponds to the line which has turned"on". This is effected in order that, when the store operations for anidentical location are consecutive and the second store operation hasarisen while the first store operation has the operand still in thebuffer 25, only a part to be altered in the second store operation,within the operand in the register in which the first store operation isqueuing, may be updated in advance. When all the lines 29 are "off", theinput pointer is cyclically incremented, and the respective store datais successively inputted to the vacant registers in the buffer 25.

Lines 30 are disposed in correspondence with the respective registers inthe buffer 25, and they indicate the validity of the respectiveregisters. The register becomes valid during the period of time from theinput of the store data till the output thereof. When any of the lines30 is "on", the output controller 26 operates to transfer the store dataqueuing in the buffer 25 to the buffer storage 15, subject to theabsence of an operand fetch request (subject to the line 8 being "off").When all the lines 30 are "on", the store data is transferred to thebuffer storage 15 irrespective of the presence or absence of the operandfetch request. Lines 31 are reset lines for flip-flops indicating thevalidity of the respecitve registers in the buffer 25, and they aredisposed in a number equal to that of the registers in the buffer 25.

FIG. 4 illustrates the details of the input controller 24. In FIG. 4,lines 4 and 10 are the same as those similarly identified in FIGS. 1-3.Lines 290-293 are respective lines in the case where the number of thelines 29 in FIG. 3 is four. Accordingly, this practical example supposesa case where the number of the registers in the buffer 25 is four.Likewise, lines 270-273 illustrate respective lines in the case wherethe number of the lines 27 in FIG. 3 is set at four.

Each of two flip-flops (hereinbelow, termed "FFs") 32 and 33 is a FF of2 bits. When a line 35 is turned "on" and a clock line TA 36 is "on",the output line 38 of an AND gate 37 turns "on", so that a 2-bit outputfrom an incrementor 34 is applied to the FF 32 through a data input line39. The 2-bit output of the FF 32 is applied to the FF 33 when a clockline TB 41 is "on". The clocks TA and TB are clocks of 2 phases. The2-bit output of the FF 33 is applied to the incrementor 34 through aline 42 and is incremented therein, and the result is reflected on theline 39. Accordingly, each time the line 35 turns "on", the values ofthe FFs 32 and 33 are updated cyclically as "00"→"01"→"10"→"11"→"00".The FFs 32 and 33, when reset by the reset line 10, are initialized tothe value "00". Thus, the FFs 32 and 33 form a four-step binary counter.

When a store request has been issued anew, the address of the storerequest is compared with the address parts of the four registers in thebuffer 25, and that one of the lines 290-293 which corresponds to theregister having that store address therein, if any, turns "on". Sincethe four registers of the buffer 25 are adapted to hold store addressesdifferent from one another, two or more of the lines 290-293 do not turn"on" at the same time. When any one of the lines 290-293 has turned"on", the output line 44 of an OR circuit 43 turns "on", and a selector45 selects the output 47 of an encoder 46. The output of the encoder 46consists of two signal lines which are encoded so as to indicate whichones of the lines 290-293 have turned "on". That is, the line 47 becomes"00" when the line 290 is "on"; "01" when the line 291 is "on"; "10"when the line 292 is "on"; and "11" when the line 293 is "on".Accordingly, the output 47 indicates the number of that register in thebuffer 25 whose store address has produced coincidence.

A decoder 48 decodes the output of the selector 45 to turn "on" one ofits output lines 49-52. The lines 49-52 are applied to respective ANDgates 53-56 along with the line 4 (the store request). When the ANDgates are enabled, they turn "on" the respective lines 270-273. Owing tothe above operations, when the store request has been issued anew andthe store address coincides with any one of the address parts of thefour registers in the buffer 25, one of the lines 270-273 correspondingto the coincident register turns "on", so that the store information canbe overlaid in the particular register.

When none of the four registers produces coincidence with the receivedstore address, the output line 58 of a NOT circuit 57 turns "on", and anAND circuit 59 is enabled by the store request, to turn "on" the outputline 35. As a result, the FF 32 is supplied with the output of theincrementor 34 and is incremented. Since, at this time, the line 44 isin the "off" state, the selector 45 selects the input line 42.Accordingly, the decoded result of the value of the FF 33 is reflectedon the lines 270-273 and instructs the input of the received operandinto a vacant register (the next register to the register havingreceived the input of an operand in the preceding store operation) inthe buffer 25.

FIG. 5 illustrates the details of the buffer 25. In FIG. 5, lines 5-7and 9 are the same as those similarly designated in FIGS. 1-3, and lines270-273 and lines 290-293 are the same as those similarly designated inFIG. 4. Each register 60-63 is constructed of a store address part 600,610, 620, 630, a store mark part 601, 611, 621, 631, a store data part602, 612, 622, 632, and a valid bit 613, 623, 633. When any one of theinput instructive lines 270-273 is "on" and a clock line TC 64 is "on",the output line of the corresponding one of the AND circuits 65-68 turns"on", and the content of the corresponding register is updated inaccordance with the data received on lines 5-7. As the updating values,the store address is given from the line 5, the store mark is appliedfrom the line 6, and the store data is received from the line 7. Thevalid bits are respectively set by the input instructive lines 270-273directly. The outputs of the address parts 600, 610, 620 and 630 of theregisters 60-63 are compared with the store address of the input line 5by comparators 69-72. When they detect coincidence, only the registershaving valid bits 603, 613, 623 and 633 are allowed to turn "on" theoutput lines 290-293 by way of AND circuits 73-76, respectively.

When one of the output lines 290-293 is "on", a corresponding one of theAND circuits 77-80 will be enabled to apply the store mark and storedata in the corresponding one of the registers 60-63 to an OR circuit81. The store mark is delivered to a line 82, and the store data to aline 83. Accordingly, in a case where, at the time of the issue of a newstore request, the store data for that store address is still beingbuffered in the store buffer 25, one of the output lines 290-293 turns"on", and the store mark and store data corresponding thereto arerespectively delivered to the lines 82 and 83. The store mark on theline 82 is applied to an OR circuit 84 and is ORed with the store markon the line 6 based on the new store request, and the result is storedin the store mark part of the register as the updated store mark. Ofcourse, each store mark of 8 bits has the same bit positions subjectedto the OR operations.

The store data on the line 83 is applied to a selector 85, which isshown in detail in FIG. 6. The store data based on the new store requestis inputted to a selector 851 through the line 7, while the store dataread from the register in the buffer 25 is inputted to a selector 852through the line 83. The selector 851 selects the data of those bytes ofthe line 7 which correspond to the bits "1" of the store mark of theline 6, and it delivers them to an OR circuit 853. The selector 852selects the data of those bytes of the line 83 which correspond to thebits "0" of the store mark of the line 6, and it delivers them to the ORcircuit 853. Thus, the updated store data merged with the store mark isdelivered from the OR circuit 853, and it is stored in the store datapart of the register.

Comparators 89-92 compare the contents of the address parts 600, 610,620, 630 of the registers 60-63 with the operand address of the operandfetch address line 9. Upon detecting a coincidence, they turn "on" theiroutput lines, and the AND result of the coincidence signals with thecorresponding valid bits 603, 613, 623, 633 are taken by AND circuits93-96. Each of the results is given as one input of the correspondingone of AND circuits 97-100 at the succeeding state. The AND circuits97-100 determine whether or not the store mark parts 601, 611, 621, 631and store data parts 602, 612, 622, 632 of the respective registers arereflected on the inputs of an OR circuit 101. Accordingly, the output ofthe OR circuit 101 provides the store mark part and store data part ofthe register which has been allowed by any of the AND circuits 97-100(as to which the AND has been established). This signifies that the datacorresponding to the fetch request exists also in the store buffer 25and is outputted. The output of the OR circuit 101 is applied to theselector 16 (FIG. 2) on lines 22 and 23.

When any one of lines 280-283 is "on", an AND circuit 102 105 transmitsthe store address part, store mark part and store data part of thecorresponding register 60-63 to an OR circuit 106. On the output lines18-20 of the OR circuit 106, accordingly, the address, mark and data ofthe register corresponding to the line 280-283 are selected. Theseoutputs of the OR circuit 106 are applied to the buffer storage 15 (FIG.2).

FIG. 7 illustrates the details of the output controller 26. In FIG. 7lines 8, 10 and 17 are the same as those similarly designated in FIGS. 2and 3, and lines 300-303, lines 280-283 and lines 310-313 arerespectively the same as those of the same reference numerals in FIG. 5.In a case where all the valid bit lines 300-303 of the four registers ofthe buffer 25 are in the "on" states, that is, where all the fourregisters hold valid store information, this situation is detected by anAND circuit 110, and the line 17 instructive of the store of the storedata into the buffer storage 15 is turned "on" from the output of an ORcircuit 111. In this case, the store of data into the buffer storage 15is executed with priority given thereto over the fetch request.

When all the lines 300-303 are not "on" but at least one of them is"on", this situation is detected by an OR circuit 112. When the outputof the OR circuit 112 is "on", the presence or absence of the operandfetch request is tested by a NOT circuit 113 and an AND circuit 114. Inthe presence of the operand fetch request, the line 8 turns "on", andthe output of the OR circuit 112 is inhibited by the NOT circuit 113 andAND circuit 114. Accordingly, only in the absence of the operand fetchrequest for the buffer storage 15, will the output of the OR circuit 112be reflected on the line 17 to cause the store of data into the bufferstorage 15. When the line 17 is "on", the store address, mark and datato be transmitted to the buffer storage 15 are applied from the registerwhich has been selected by the lines 280-283 to the buffer 25.

The signal of the store instructive line 17 and the signals of theoutput instructive lines 280-283 are respectively subjected to an ANDoperation by AND circuits 115-118, and the results are latched for phaseadjustments by a FF 119. The output 310-313 of the FF 119 turns "off"the valid bit of the register in the buffer 25 which has been instructedto deliver the outputs.

Each of FFs 120 and 121 is an FF of 2 bits. More particularly, when boththe line 17 and a timing line TD 125 are "on", the output of an ANDcircuit 123 turns "on" to update the content of the FF 120. The updatedvalue of the FF 120 is given by an incrementor 122, and it is equal tothe content of the FF 121 with 1 (one) added thereto. The FFs 120 and121 are reset to the initial value "00" by the reset line 10.Accordingly, each time the line 17 turns "on", the contents of the FFs120 and 121 are incremented cyclically as "00"→"01"→"10"→"11"→"00". Theoutput of the FF 121 is decoded by a decoder 124, and the decoder 124turns "on" one of the output instructive lines 280-283 corresponding tothe above output.

Referring to FIG. 5 again, when one of the output instructive lines280-283 is turned "on", the corresponding one of the AND circuits102-105 is enabled, and the store address, store mark and store data inthe register are transmitted to the buffer storage 15. At the same time,the valid bit part of the particular register is turned "off" by thecorresponding lines 310-313.

FIG. 8 illustrates the details of the selector 16 in FIG. 2. In FIG. 8,lines 11, 21, 22 and 23 are the same as those similarly identified inFIG. 1 and so forth. FIG. 8 shows an example in which the fetch/storedepth of the buffer storage 15 is 8 bytes. Data of 8 bytes fetched fromthe buffer storage 15 (FIG. 2) is set in a register 161 of 8 bytesthrough the line 21. The store mark of 8 bits and the data of 8 bytes,which have been fetched from the store buffer 14, are respectively setin a register 162 of 8 bits and a register 163 of 8 bytes. A selector164 selects the data of those bytes of the register 161 which correspondto the bits "0" of the mark of the register 162, and it delivers them toan OR circuit 166. A selector 165 selects the data of those bytes of theregister 163 which correspond to the bits "1" of the mark of theregister 162, and it delivers them to the OR circuit 166. Thus, the datafrom the buffer storage 15 and the store buffer 14 merged with the storemark are provided from the OR circuit 166 as fetch data meeting thefetch request.

According to the present invention, the competition of a store requestand an instruction or operand fetch request for a storage can bereduced, so that the delay of instruction or operand fetch attributed tothe competition is shortened advantageously.

While we have shown and described an embodiment in accordance with thepresent invention, it is understood that the same is not limited theretobut is susceptible of numerous changes and modifications as known to aperson skilled in the art, and we therefore do not wish to be limited tothe details shown and described herein but intend to cover all suchchanges and modifications as are obvious to one of ordinary skill in theart.

What is claimed is:
 1. A storage system comprising:main storage meansfor storing data; cache storage means coupled to said main storage meansfor storing a portion of the data stored in said main storage means,said cache storage means operating to store data in response to receiptof a write pulse and a store address and to read out data in response toreceipt of a fetch request and a fetch address; request generating meansfor generating a fetch address together with a fetch request when datais to be fetched from said cache storage means, and for generating astore address, store data and a store mark together with a store requestwhen data is to be stored in said storage means, said store markidentifying that portion of the store data to be stored in said cachestorage means; and store buffer means coupled to said cache storagemeans and said request generating means for temporarily storing databefore it is stored in said cache storage means, including a pluralityof register means for storing the store address, store data and storemark from said request generating means into one of said register meansin response to receipt of the store request for said request generatingmeans input control means for specifying in regular order the registermeans to store the store address, store data and store mark accompaniedby the store request, in response to said store request, means fortransferring said store address, store data and store mark stored insaid register means to said cache storage means along with a write pulseat a time when no fetch request is being generated by said requestgenerating means, output control means for specifying in regular orderthe register means storing the store address, store data and store markto be transferred to said cache storage means, comparison means forcomparing the fetch address accompanied by the fetch request from saidrequest generating means and the store addresses stored in therespective register means, and for providing coincidence signalsindicating coincidence between said addresses, and output meansresponsive to the coincidence signal from the comparison means forcontrolling said transferring means to output the store data and storemark from the register means which said comparison means indicates hasprovided said coincidence; and means for merging the data read from saidcache storage means in response to the fetch request and the portion ofsaid store data outputted under control of said output means andidentified by said store mark outputted from said store buffer means. 2.A storage system comprising:main storage means for storing data; cachestorage means coupled to said main storage means for storing a portionof the data stored in said main storage means, said cache storage meansoperating to store data in response to receipt of a write pulse and astore address and to read out data in response to receipt of a fetchrequest and a fetch address; request generating means for generating afetch address together with a fetch request when data is to be fetchedfrom said cache storage means, and for generating a store address, storedata and a store mark together with a store request when data is to bestored in said storage means, said store mark identifying that portionof the store data to be stored in said cache storage means; and storebuffer means coupled to said cache storage means and said requestgenerating means for temporarily storing data before it is stored insaid cache storage means, including a plurality of register means forstoring the store address, store data and store mark from said requestgenerating means into one of said register means in response to receiptof the store request for said request generating means input controlmeans for specifying in regular order the register means to store thestore address, store data and store mark accompanied by the storerequest, in response to said store request, means for transferring saidstore address, store data and store mark stored in said register meansto said cache storage means along with a write pulse at a time when nofetch request is being generated by said request generating means,output control means for specifying in regular order the register meansstoring the store address, store data and store mark to be transferredto said cache storage means, comparison means for comparing the storeaddress accompanied by the store request from said request generatingmeans and the store addresses stored in the respective register meansand for providing coincidence signals indicating coincidence betweensaid addresses; said input control means includes means responsive tothe coincidence signal being provided from the comparison means forspecifying the register means which said comparison means indicates hasprovided said coincidence; and said store buffer means further includingmeans for merging the store data and store mark stored in said registermeans which said comparison means indicates has provided saidcoincidence with the store data and store mark from said requestgenerating means, and means for storing the merged results again intosaid register means specified by said input control means.
 3. A storagesystem comprising:main storage means for storing data; cache storagemeans coupled to said main storage means for storing a portion of thedata stored in said main storage means, said cache storage meansoperating to store data in response to receipt of a write pulse and astore address and to read out data in response to receipt of a fetchrequest and a fetch address; request generating means for generating afetch address together with a fetch request when data is to be fetchedfrom said cache storage means, and for generating a store address, storedata and a store mark together with a store request when data is to bestored in said storage means, said store mark identifying that portionof the store data to be stored in said cache storage means; and storebuffer means coupled to said cache storage means and said requestgenerating means for temporarily storing data before it is stored insaid cache storage means, including a plurality of register means forstoring the store address, store data and store mark from said requestgenerating means into one of said register means in response to receiptof the store request for said request generating means input controlmeans for specifying in regular order the register means to store thestore address, store data and store mark accompanied by the storerequest, in response to said store request, means for transferring saidstore address, store data and store mark stored in said register meansto said cache storage means along with a write pulse at a time when nofetch request is being generated by said request generating means,output control means for specifying in regular order the register meansstoring the store address, store data and store mark to be transferredto said cache storage means, first comparison means for comparing thestore address accompanied by the store request from said requestgenerating means and the store addresses stored in the respectiveregister means and for providing coincidence signals indicatingcoincidence between said addresses; second comparison means forcomparing the fetch address accompanied by the fetch request from saidrequest generating means and the store addresses stored in therespective register means, and for providing coincidence signalsindicating coincidence between said addresses; said input control meansincluding means responsive to the coincidence signal from the firstcomparison means for specifying the register means which said firstcomparison means indicates has provided said coincidence; means formerging the store data and store mark stored in said register meanswhich said first comparison means indicates has provided saidcoincidence signal with the store data and store mark from said requestgenerating means, and means for storing the merged results again intosaid register means specified by said input control means; and outputmeans responsive to the coincidence signal from the second comparisonmeans for controlling said transferring means to output the store dataand store mark from the register means which said second comparisonmeans indicates has provided said coincidence signal; and means formerging the data read from said cache storage means in response to thefetch request and the portion of said store data outputted under controlof said output means and identified by said store mark outputted fromsaid store buffer means.